1. Field of the Invention
The present invention relates, in general, to testing of integrated circuits and, more specifically, to a method and circuit for scan testing integrated circuits.
2. Description of Related Art
Scan circuits consist of logic and memory elements that are configurable in a scan mode and a capture mode. Scannable memory elements are organized in scan chains. Scan testing of scan circuits generally involves shifting a test pattern into scan chains of scannable memory elements in a circuit, capturing the response of the circuit during a capture cycle and then shifting the test response out of the circuit for analysis. The memory elements are configured in “shift mode” when test patterns are loaded and when test responses are unloaded and are configured in “capture mode” during the capture cycle. The capture mode corresponds to the normal operational mode of the memory elements.
Preferably, the clock used during capture cycle is an at-speed or system clock, in which the clock period is substantially the same as that used during normal operation of the circuit. In some cases, a higher clock frequency is desirable in order to compensate for favorable process and operating conditions.
It is known to be advantageous to apply several clock cycles during the capture phase in order to test for complex failure mechanisms such as power supply noise, IR-drop, signal coupling, etc., requiring an at-speed test. Applying several clock pulses during the capture phase is also required to test multi-cycle signal paths (MCPs).
Some scan testing methods are known to configure memory elements in capture mode for more than one capture clock cycle. However, doing so reduces fault coverage and increases computational effort (sequential fault simulation is required for any number of capture clock cycle in excess of one) because the final input stimulus applied to the circuit logic is a function of the circuit logic itself, not the test data loaded into the scan chains.
Applicants' prior U.S. Pat. Nos. 6,327,684 and 6,442,722, incorporated herein by reference, describe and claim methods in which memory elements are configured in a shift mode for all but the last clock cycle of the capture phase. However, these methods require a relatively complex interface between the scan chains and the test controller.